A capacitor is one of the components essential for composing an electronic circuit. Thus, a capacitor in a monolithic structure is useful for producing a semiconductor device circuit or an integrated circuit (an IC). Since the magnitude of electrostatic capacity of a capacitor is proportional to the magnitude of the area of two electrodes which face each other, leaving a dielectric layer therebetween, various efforts have been used to increase the area of two electrodes composing a capacitor in a monolithic structure.
Among plural pieces of prior act in this category, a U.S. Pat. No. 5,623,243 granted for Hirohito Watanabe et al. on Apr. 22, 1997 can be a piece of information disclosing the technology relating to a semiconductor device acting as a capacitor in which a polycrystalline Si layer having a surface with micro roughness caused by Si grains which are generated by employing an LPCVD process which is conducted at a specific temperature condition in which the crystal state of the deposited Si film is transiting from the amorphous phase to the polycrystalline phase, is employed as one of the electrodes.
Referring to drawings, an exemplary process for producing a semiconductor device acting as a capacitor in which a polycrystalline Si layer having a rugged surface is employed for one of the two electrodes which face each other, leaving a dielectric layer therebetween, will be described below.
Referring to FIG. 1, a CVD process is conducted to produce an SiO.sub.2 layer (1) having an approximate thickness of 800 nm on a conductive Si substrate (0). A CVD process is conducted to produce an Si.sub.3 N.sub.4 layer (2) having an approximate thickness of 100 nm on the SiO.sub.2 layer (1).
Referring to FIG. 2, a photo lithography process is conducted to produce a recess having an approximate diameter of 200 nm and an approximate depth of 900 nm from the top surface of the Si.sub.3 N.sub.4 layer (2). For this purpose, an anisotropic etching process is employed to etch the Si.sub.3 N.sub.4 layer (2) and the SiO.sub.2 layer (1) from a selected area remained uncovered by a photo resist mask. A mixture of C.sub.4 F.sub.8, CO, Ar and O.sub.2 can be employed as the etchant gas. As a result, the top surface of the conductive Si substrate (0) is exposed at a location corresponding to the recess. A CVD process is conducted to produce a polycrystalline Si layer (3) containing an impurity having a conductivity identical to that of the Si substrate (0) to an approximate concentration of 5.times.10.sup.20 cm.sup.-3, on the Si.sub.3 N.sub.4 layer (2), which resultantly buries the recess produced in the foregoing process. The thickness of the conductive polycrystalline Si layer (3) is approximately 300 nm on top of the surface of the Si.sub.3 N.sub.4 layer (2).
Referring to FIG. 3, the conductive polycrystalline Si layer (3) is etch-backed to expose the top surface of the Si.sub.3 N.sub.4 layer (2). Cl.sub.2 can be employed as the etchant gas. In this manner, the conductive polycrystalline Si layer (3) is remained in the recess in the shape of a conductive plug electrically connected with the conductive Si substrate (0).
Referring to FIG. 4, a CVD process is conducted to produce an SiO.sub.2 layer (4) having an approximate thickness of 600 nm on the Si.sub.3 N.sub.4 layer (2) and the conductive Si plug (3).
Referring to FIG. 5, a photo lithography process is conducted to produce a recess having an approximate diameter of 300 through 500 nm and an approximate depth of 300 nm from the top surface of the SiO.sub.2 layer (4). For this purpose, a mixture of CF.sub.4, CHF.sub.3, and Ar can be employed as the etchant gas. As a result, the top surface of the plug-shaped conductive polycrystalline Si layer (3) is exposed. A CVD process is conducted to produce a polycrystalline Si layer (5) containing an impurity having a conductivity identical to that which is contained in the conductive polycrystalline Si plug (3) to an approximate concentration of 5.times.10.sup.20 cm.sup.-3 and having an approximate thickness of 50 nm, on top of the conductive polycrystalline Si plug (3) and the SiO.sub.2 layer (4). Further, an LPCVD process is conducted in SiH.sub.4 at a pressure of 0.2 torr and at a temperature of 570.degree. C. to produce a conductive polycrystalline Si layer (6) having a rugged surface and having an approximate thickness of 50 nm on top of the conductive polycrystalline Si layer (5). The production of the rugged surface is caused by coexistence of amorphous regions and polycrystalline grains in the conductive polycrystalline Si (5) having a rugged surface (6) in which an amorphous phase is transiting to a polycrystalline phase. (See a paper, IEDM 90-661, entitled "RUGGED SURFACE POLY-Si ELECTRODE AND LOW TEMPERATURE DEPOSITED Si.sub.3 N.sub.4 FOR 64-MBIT AND BEYOND STC DRAM CELL" written by M. Yoshimaru et al. and published by IEEE on 1990 and available as CH 2865-4/90/0000-0659 at IEEE.) A CVD process is conducted to produce an SiO.sub.2 layer (7) having an approximate thickness of 300 nm on top of the conductive polycrystalline Si layer (6) having a rugged surface.
Referring to FIG. 6, SiO.sub.2 particles (8) are deposited in space remained among the top surface of the conductive polycrystalline Si layer (5) and each gain composing the conductive polycrystalline Si layer (6) having a rugged surface, during the foregoing CVD process for producing the conductive polycrystalline Si layer (6) having a rugged surface. Since the SiO.sub.2 particles (8) deposited on the area in which the monolithic capacitor is not produced, causes serious problems in a later process, the scope of FIG. 6 is limited to the area in which the monolithic capacitor is not produced.
Referring to FIG. 7, an anisotropic etching process is conducted to etch-back the SiO.sub.2 layer (7) until the conductive polycrystalline Si layer (6) having a rugged surface is exposed. A mixture of CF.sub.4, CHF.sub.3 and Ar can be employed as the etchant gas.
Referring to FIG. 8, employing the SiO.sub.2 layer (7) as an etching mask, an anisotropic etching process is conducted to remove the conductive polycrystalline Si layer (6) having a rugged surface and the conductive polycrystalline Si layer (5) from the top of the SiO.sub.2 layer (4). For this process, Cl.sub.2 can be employed as the etchant gas. Since the SiO.sub.2 particles (8) deposited in space remained among the top surface of the conductive polycrystalline Si layer (5) and each grain composing the conductive polycrystalline Si layer (6) having a rugged surface acts as a type of etching mask during the foregoing etching process, plural pillars of the conductive polycrystalline Si layer (5) remain on top of the SiO.sub.2 layer (4).
Referring to FIG. 9, an isotropic etching process is conducted to entirely remove the SiO.sub.2 layer (7) and the SiO.sub.2 layer (4). For this process, HF can be employed as the etchant. During this etching process, however, the foregoing plural pillars of the conductive polycrystalline Si layer (5) are disengaged from the SiO.sub.2 layer (4) to become dust floating in the etchant liquid, which dust is finally deposited again on the surface of an Si wafer to finally cause adverse results for the throughput of a method for producing a semiconductor device which acts as a capacitor.
Produced in this manner is one of the electrodes of a monolithic capacitor, the electrode having the shape of a vertical cylinder having an open end upward and a closed end downward made of a conductive polycrystalline Si layer (5) covered by the conductive polycrystalline Si layer (6) having a rugged surface, and resultantly having a large magnitude of the surface area thereof.
Referring to FIG. 10, a CVD process is conducted to produce a dielectric layer (9) e.g. an Si.sub.3 N.sub.4 layer, a piled layer of SiO.sub.2 /Si.sub.3 N .sub.4 /SiO.sub.2 and the like to cover the electrode having the shape of a vertical cylinder having an open end upward and a closed end downward made of a conductive polycrystalline Si layer (5) covered by the conductive polycrystalline Si layer (6) having a rugged surface produced by the foregoing series of steps. A CVD process is conducted to produce a conductive polycrystalline Si layer (10) to cover the dielectric layer (9). The conductivity of the conductive polycrystalline Si layer (10) is free. Needless to emphasize, the conductive polycrystalline Si layer (10) is extended to produce an electrode of a terminal (not shown) of the monolithic capacitor produced by the foregoing series of steps. As a final step, a passivation process is usually conducted.
The foregoing description has elaborated the drawbacks which accompanies the foregoing method available in the prior art for producing a semiconductor device which acts as a monolithic capacitor, which monolithic capacitor has a large magnitude of electrostatic capacity due to a large area of one of the electrodes composing the monolithic capacitor.